OS ASSIGNMENT – 01
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GAJJAR PREMAL
Q - 1.1 List and briefly define the four main elements of a computer.
ANS -
(1) Processor
- Controls the operation of computer & performs its data processing function.
- when their one processor called as CPU.
(2) Main Memory
- store data & programs.
- memory is volatile – data will be lost when computer shut down.
- contents of disk memory are same even shut down called real or primary memory.
(3) I/0 modules
- move data between computer and its external environment.
- external environment consists of devices including secondary memory devices & terminals.
(4) System bus
-Provides for communication among processors, main memory & I/O modules.
Q – 1.2 Define the two main categories of processor registers.
ANS -
(1) User – Visible Registers
- Enable the machine or assembly language programmer to minimize main memory references by
optimizing register use and for high level languages compiler will do this task.
- ex. Data and address registers, index registers, segment pointer, stack pointer.
(2) Control & Status registers
- used by the processor to control the operation of processor & by privileged as routines to control the
execution of programs.
- ex. Program counter, instruction register, flags register
Q – 1.3 In general terms, what are the four distinct actions that a machine instruction can specify?
ANS -
(1) processor – memory
- data may be transfer from processor to memory or memory to processor.
(2) processor – I/O
- data may be transferred between peripheral devise (I/O) to processor.
(3) data processing
- perform arithmetic or logic operation on data.
(4) control
- An instruction may specify that the sequence of execution be altered called control.
- suppose processor fetch instruction from location 149, it specify that next instruction from location
182. so processor sets pc to 182 so next instruction fetch from 182 instead 150.
Q – 1.4 What is an interrupt?
ANS -
- A mechanism by which other modules (i/o,memory) may interrupt the normal sequence of the
program to improve processor utilization.
Class of interrupts -
(1) programme – ex. division by zero.
(2) timer – generated by timer for perform certain function on regular basis.
(3) I/O – generated by i/o controller, to signal normal completion of an operation or variety of
signal error condition. ex. In Printer page empty load trey.
(4) hardware failure – such as power failure or memory parity error.
Q – 1.5 How are multiple interrupts dealt with?
ANS -
When at running of a single interrupt execution the other one interrupt is occur at same time called
multiple interrupts.
For dealing with it there are two approaches -
(1) disable interrupts while an interrupts is being processed.
- Its called sequential interrupt processing.
- It means that processor ignores any any of new interrupt request signal. In generally new interrupt is
pending and processor will check after completion of running interrupt.
- drawback – the first batch of input has not been proceed before the second batch arrives, data will be
lost because of overflow of buffer.
(2) allow an higher priority interrupt during the time of lower priority interrupt execution.
- it called nested interrupt processing.
- ex. System with 3 i/o devices – printer, disk, communication line. Priorities are 2, 4, 5 respectively so
when any interrupt are arrived at interrupt execution then as per its priority it can be executed.
Q – 1.6 What characteristics distinguish the various elements of a memory hierarchy?
ANS -
there are three characteristics of memory are Namely, Capacity, Access time and Cost.
The various characteristics which distinguish in between of memory hierarchy elements are:
(1) Faster access time, greater cost per bit
eg. registers & cache memory
They have faster access time so higher cost per bit & low capacity
(2) Greater capacity, smaller cost per bit
eg. main memory or RAM
They have moderate access time, moderate cost per bit &
(3) Greater capacity, slower access speed
eg. magnetic disk & magnetic tape
They have high capacity, low cost per bit & slower access.
Q – 1.7 What is cache memory?
ANS -
cache memory - The part of Random Access Memory or Main Memory that is easily accessible to the
processor is called as cache memory.
- As the microprocessor processes data, it looks first in the cache memory and if it finds the data in
cache memory, then in main memory, it takes less time for that compare with RAM.
- The cache contains a copy of a portion of random access memory.
- Cache memory is intended to provide memory access time approaching that of the fastest memories
available.
- As compare with registers memory, cache memory is low cost per bit and has faster access time.
Q – 1.8 List and briefly define three techniques for I/O operations.
ANS -
Programmed I/O -
- Programmed input/output is a method of transferring data between the CPU and Input/Output
peripherals.
- the processor is responsible for extracting data from main memory for output and storing data in main
memory for input.
- The CPU issues a command then waits for I/O operations to be complete.
the instruction set includes I/O instructions in the following categories:
- Control: Used to activate an external device and tell it what to do.
For example, a magnetic-tape unit may be instructed to rewind or to move forward one record.
- Status: Used to test various status conditions associated with an I/O module and its peripherals.
- Transfer: Used to read and/or write data between processor registers and external devices.
Interrupt-driven I/O
- in programmed I/O The processor, while waiting, must repeatedly interrogate the status of the I/O
module. As a result, the performance level of the entire system is severely degraded.
- I/O command to a module and then go on to do some other useful work.
- The I/O module will then interrupt the processor to request service when it is ready to exchange data
with the processor.
- The processor then executes the data transfer, as before, and then resumes its former processing.
Direct Memory Access
- Thus both of the above forms of I/O suffer from two inherent drawbacks:
1. The I/O transfer rate is limited by the speed with which the processor can test and service a device.
2. The processor is tied up in managing an I/O transfer; a number of instructions must be executed for
each I/O transfer.
- The DMA function can be performed by a separate module on the system bus or it can be
incorporated into an I/O module.
- the processor wishes to read or write a block of data, it issues a command to the DMA module, by
sending to the DMA module the following information:
• Whether a read or write is requested
• The address of the I/O device involved
• The starting location in memory to read data from or write data to
• The number of words to be read or written
DMA is far more efficient than interrupt- driven or programmed I/O.
Q – 1.9 What is the distinction between spatial locality and temporal locality?
ANS -
- The concept that a resource that is referenced at one point in time will be referenced again sometime
in the near future is called as temporal locality.
- If a particular memory location is referenced at a particular time, then it is likely that nearby
memory locations will be referenced in the near future is called as spatial locality.
Q – 1.10 In general, what are the strategies for exploiting spatial locality and temporal locality?
ANS -
- Temporal locality is exploited by keeping recently used instruction and data values in
cache memory and by exploiting a cache hierarchy.
- Spatial locality is generally exploited by using larger cache blocks and by
incorporating pre-fetching mechanisms into the cache control logic.
4. Answer the following Problems: 1.1, 1.3, 1.5, 1.7, 1.9
1.1 Suppose the hypothetical processor of Figure 1.3 also has two I/O instructions:
0011 . Load AC from I/O
0111 . Store AC to I/O
In these cases, the 12-bit address identifies a particular external device. Show the program
execution (using format of Figure 1.4) for the following program:
1. Load AC from device 5.
2. Add contents of memory location 940.
3. Store AC to device 6.
Assume that the next value retrieved from device 5 is 3 and that location 940 contains
a value of 2.
Memory (contents in hex):
300: 3000
301: 6000
302: 9000
1: 3000 . IR
2: 3 . AC
3: 6000 . IR
4: 3 + 2 = 5 . AC
5: 9000 . IR
6: AC . Device 6
1.3 Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of
two fields. The first byte contains the opcode and the remainder an immediate operand
or an operand address.38
CHAPTER 1 / COMPUTER SYSTEM OVERVIEW
a. What is the maximum directly addressable memory capacity (in bytes)?
b. Discuss the impact on the system speed if the microprocessor bus has
1. a 32-bit local address bus and a 16-bit local data bus, or
2. a 16-bit local address bus and a 16-bit local data bus.
c. How many bits are needed for the program counter and the instruction register?
Ans:
a. 2^24 = 16 MBytes
b. (1) If the address bus is 32 bits, the whole address can be transferred at once and decoded in
memory. But the data bus is only 16 bits, so it will require 2 cycles to fetch a 32-bit instruction or
operand.
(2) The 16 bits of the address placed on the address bus can't access the whole memory. Thus a more
complex memory interface control is needed to latch the first part of the address and then the second
part (since the microprocessor will -2-end in two steps). For a 32-bit address, one may assume the first
half will decode to access a "row" in memory, while the second half is sent later to access a "column"
in memory. In addition to the two-step address operation, the microprocessor will need 2 cycles to fetch
the 32 bit instruction/operand.
c. The program counter must be at least 24 bits.
1.5 Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input
clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four
input clock cycles. What is the maximum data transfer rate across the bus that this
microprocessor can sustain in bytes/s? To increase its performance, would it be better to make its
external data bus 32 bits or to double the external clock frequency supplied to the
microprocessor? State any other assumptions you make and explain. Hint: Determine the
number of bytes that can be transferred per bus cycle.
1/8 × 10^6 = 125 ns
4 clk cycles of 8 MHz Bus cycle = 4 × 125 ns = 500 ns
2 bytes transferred every 500 ns; thus transfer rate = 4 MBytes/sec
Clock cycle = Doubling the frequency may mean adopting a new chip manufacturing technology;
doubling the external data bus means wider on-chip data bus drivers/latches and modifications to the
bus control logic. In the first case, the speed of the memory chips will also need to double not to slow
down the microprocessor; in the second case, the "wordlength" of the memory will have to double to be
able to send/receive 32-bit quantities.
1.7 In virtually all systems that include DMA modules, DMA access to main memory is
given higher priority than processor access to main memory. Why?
If a processor is held up in attempting to read or write memory, usually no damage occurs except a
slight loss of time. However, a DMA transfer may be to or from a device that is receiving or sending
data in a stream (e.g., disk or tape), and cannot be stopped. Thus, if the DMA module is held up (denied
continuing access to main memory), data will be lost.
1.9 A computer consists of a CPU and an I/O device D connected to main memory M via a shared
bus with a data bus width of one word. The CPU can execute a maximum of 106 instructions per
second. An average instruction requires five processor cycles, three of which use the memory bus.
A memory read or write operation uses one processor cycle. Suppose that the CPU is
continuously executing “background” programs that require 95% of its instruction execution
rate but not any I/O instructions.APPENDIX 1A / PERFORMANCE CHARACTERISTICS OF
TWO-LEVEL MEMORIES
Assume that one processor cycle equals one bus cycle. Now suppose that very large blocks of data
are to be transferred between M and D.
a. If programmed I/O is used and each one-word I/O transfer requires the CPU to execute two
instructions, estimate the maximum I/O data transfer rate, in words per second, possible through
D.
b. Estimate the same rate if DMA transfer is used.
a. The processor can only devote 5% of its time to I/O. Thus the maximum I/O instruction execution
rate is 106 × 0.05 = 50,000 instructions/second. The I/O transfer rate is therefore 25,000 words/second.
b. The number of machine cycles available for DMA control is 10^6 × (0.05 × 5 +
0.95 × 2) = 2.15 × 10^6.
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