VERILOG CODE FOR HALF ADDER WITH TEST BENCH

                    VERILOG CODE FOR HALF ADDER WITH TEST BENCH 


VERILOG CODE FOR HALF ADDER:

module ha(a, b, sum, carry);

input a;

input b;

output sum;

output carry;

assign carry=a&b;                          

assign sum=a^b;                            

endmodule


TEST BENCH:

module halfaddert_b;

reg a;

reg b;

wire sum;

wire carry;

ha uut ( .a(a),.b(b),.sum(sum), .carry(carry));

initial begin

#10 a=1′b0;b=1′b0;                      

#10 a=1′b0;b=1′b1;                      

#10 a=1′b1;b=1′b0;                      

#10 a=1′b1;b=1′b1;                        

#10$stop;

end

endmodule