MOORE OVERLAPPING TYPE SEQUENCE 1010 PROGRAM WITH TEST BENCH CODE IN VERILOG:

MOORE OVERLAPPING TYPE SEQUENCE 1010 PROGRAM WITH TEST BENCH CODE IN  VERILOG:


PROGRAM:

module mor_over_1010 (input data,input clock,input reset,output reg seq_detect);
parameter A=0,B=1,C=2,D=3,E=4;
reg [2:0] state, next;
always@(posedge clock or negedge reset)
begin
if (!reset) state <= A;
else state <= next;
end
always@(state or data)
begin
case (state)
A: begin seq_detect = 0;
if  (!data) next = A;
else  next = B;end
B: begin seq_detect = 0;
if  (!data) next = C;
else next = B;end
C: begin seq_detect = 0;
if  (!data) next = A;
else next = D;end
D: begin seq_detect = 0;
if  (!data) next = E;
else next = B;end
E: begin seq_detect = 1;
if  (!data) next = A;
else next = D;end
endcase
end
//assign seq_detect = (state == E);
endmodule


TEST BENCH:

module mor_over_tb;
reg clock,reset,data;
wire seq_detect;
mor_over_1010 m1 (.clock(clock),.reset(reset),.data(data),.seq_detect(seq_detect));
initial
begin
$monitor($time, ,"c=%b",clock, ,"r=%b",reset, ,"d=%b",data, ,"s=%b",seq_detect);
reset = 1'b1; data = 1'b0;
#2 reset = 0; #3 reset = 1;
#2 data = 1'b1;
#2 data = 1'b0;
#2 data = 1'b1;
#2 data = 1'b0;
#2 data = 1'b1;
#2 data = 1'b0;
#2 data = 1'b1;
#2 data = 1'b0;
#2 data = 1'b1;
#2 data = 1'b0;
#10 $finish;
end
initial
clock = 0;
always #1 clock = ~clock;
endmodule