Verilog Code to implement 8 bit Johnson Counter with Testbench

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The following verilog code will generate a synthesis logic for 8 bit Johnson Counter.

The Johnson Counter is also refereed as Twisted Ring Counter or Möbius counter

The Design module for Johnson Counter is verified by Test-bench

• Verilog Code for 8 bit Johnson Counter or Twisted Ring Counter

module johnson(Resetn, Clock, Q);
input Resetn, Clock;
output[7:0] Q;
reg [7:0] Q;
always @(negedge Resetn or posedge Clock)
if(!Resetn)
Q <= 0;
else
Q <= {{Q[6:0]},{~Q[7]}};
endmodule

• Test Bench for 8 bit Johnson Counter or Twisted Ring Counter

module johnsontstbnch;
reg rst,clk;
wire [7:0]q;
johnson jon (rst,clk,q);

initial
begin
clk=0;
rst = 0;

$monitor($time, ,”c=%b”,clk, , ,”r=%b”,rst, , ,”q=%b”,q);
#6 rst =1;
end

always #2 clk = ~clk;

initial #68 $finish;

endmodule