VERILOG CODE FOR S-R FLIP FLOP (BEHAVIORAL MODEL)

                                 VERILOG CODE FOR S-R FLIP FLOP
                                              (BEHAVIORAL MODEL)


VERILOG CODE FOR S-R FLIP FLOP:


module SR_flipflop(q,q1,r,s,clk);
output q,q1;
input r,s,clk;
reg q,q1;
initial

//Initial Block is used to set the values of q and q1 initially because then these values will be used as feedback in the always block. Initial Block is executed only once in the code.

begin
q=1'b0; q1=1'b1;                                       // q is set to 0 and q1 is set to 1.
end
always @(posedge clk)
begin
case({s,r})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=1'bx; q=1'bx; end
endcase
end
endmodule