verilog code for full adder with test bench

VERILOG CODE FOR FULL ADDER WITH TEST BENCH USING DATA-FLOW AND USING STRUCTURAL

PROGRAMME :


USING DATA-FLOW

module fulladderdtf
(input a,b,c,
output s,y);
assign s=a^b^c,
y=a&b||a&c||b&c;
endmodule

TEST BENCH
module fulladder_tb;
reg a,b,c;
wire s,y;
fulladderdtf m1(a,b,c,s,y);
initial
begin
$monitor($time, ,"a=%b",a, ,"b=%b",b, , "c=%b",c, ,"s=%b",s, ,"y=%b", y);
a=0;b=0;c=0;
#5 a=0; b=0; c=1;
#5 a=0; b=1; c=0;
#5 a=0; b=1; c=1;
#5 a=1; b=0; c=0;
#5 a=1; b=0; c=1;
#5 a=1; b=1; c=0;
#5 a=1; b=1; c=1;
end
endmodule

USING STRUCTURAL
module fa(input a,b,c, output s,y);
wire d,e,f;
xor(s,a,b,c);
and(d,a,b);
and(e,b,c);
and(f,a,c);
or(y,d,e,f);
endmodule