VERILOG CODE FOR FULL SUBSTRECTOR WITH TEST BENCH USING DATA-FLOW AND USING STRUCTURAL

VERILOG CODE FOR FULL SUBSTRECTOR WITH TEST BENCH USING DATA-FLOW AND USING STRUCTURAL

USING DATA-FLOW

module fullsub
(input x,y,z,
output d,b);
assign d=(~x&~y&z)||(~x&y&~z)||(x&~y&~z)||(x&y&z),
b=(~x&~y&z)||(~x&y&~z)||(~x&y&z)||(x&y&z);
endmodule

TEST BENCH

module fullsub_tb;
reg a,b,c;
wire bor,diff;
fullsub m1(a,b,c,bor,diff);
initial begin
$monitor($time, ,"a=%b",a,"b=%b",b,"c=%b",c,"y=%b",bor,"d=%b",diff);
a=0;b=0;c=0;
#5 a=0;b=0;c=1;
#5 a=0;b=1;c=0;
#5 a=0;b=1;c=1;
#5 a=1;b=0;c=0;
#5 a=1;b=0;c=1;
#5 a=1;b=1;c=1;
end
endmodule

USING STRUCTURAL

module fullsubstrect(a, b, c, diff, borr);
input a,b,c;
output diff,borr;
wire d,e,f;
xor(diff,a,b,c),
(d,a,b);
and(e,c,~d),
(f,~a,b);
or (borr,e,f);
endmodule